Parallel Stochastic Computing Architecture for Computationally Intensive Applications

Stochastic computing requires random number generators to generate stochastic sequences that represent probability values. In the case of an 8-bit operation, a 256-bit length sequence is required, which results in latency issues. this paper, architecture proposed address issue by employing parallel linear feedback shift registers (LFSRs). The reduces generation process without losing accuracy. addition, achieves area efficiency reducing 69% flip-flops and 70.4% LUTs compared shared LFSRs, 74% 58% applying multiple LFSRs with same computational time.